At Rambus, we are turning incredible possibilities into everyday reality by helping to deliver the innovations that greatly impact the world we live in. We create leading-edge semiconductor and IP products, spanning memory and interfaces to security to smart sensors and lighting. Our products are integrated into tens of billions of devices and systems around the globe, running critical applications for Big Data, Internet of Things (IoT), mobile, consumer and media platforms.
And our history runs deep – we have been a staple in Silicon Valley for the past 25 years and are continually anticipating key technology trends and are developing innovations that drive market changes. From a pure IP provider to becoming a fabless chipmaker, Rambus is evolving to address critical challenges in the semiconductor industry.
As a dynamic organization, we are always seeking to hire exceptional talent to join some of the brightest inventors and engineers in the world to explore their passions to develop products that have real life impact. As well, Rambus benefits are among the most comprehensive and competitive in the industry.
Memory and interfaces are in our DNA. Leveraging over two decades of high-speed circuit design leadership, we make high-performance, low-power memory and serial link interface chips and IP cores to meet the needs of increasingly diverse enterprise and mobile applications. Featuring proven IP and advanced technology, our product families include server DIMM chipsets, R+ DDRn PHYs and R+ Serial Link PHYs.
Architecture, design, implementation and debugging of High speed, highly integrated memory subsystems. Candidate will have opportunities within the complete verification lifecycle, from system-level and chip verification architecture to tape out, including post-silicon validation. Responsibilities involves pre/post silicon test planning, testbench development using SV/UVM, assertion development and formal verification/property checking. Ability to understand/interpret system/chip level requirements, system/block level partitioning, and ability to develop/deliver test plans for functional/analog performance, scalable testbench, test case development on time. Additionally, coverage model development, Power simulations, debugging, coverage closure and Gate level sims will be part of the ongoing day to day tasks. Candidate will be working in the digital verification team, collaborating with the digital and analog design teams, analog modeling, characterization and DFT teams throughout the SoC cycle including post-silicon validation.
- Create block level verification plans, coding and analysis of functional coverage
- Create verification components in SV, UVM, C/C++
- Handle block level verification independently.
- Debug issues and present / discuss problems with designers independently
- Run regression, achieve code coverage and functional coverage goals
- Run netlist verification without and with SDF
- BS/MS CE/EE/CS with 7+ years of experience in ASIC/SoC verification
- Expert knowledge in verification tools, languages, Methodologies (Systemverilog, UVM, Assertions)
- Background in test bench architecture (both directed and random-constrained testing, transactors, checkers, assertions, coverage models) with a focus on flexibility and reuse.
- Independent, self-motivated, professional attitude and strong desire to succeed
- Must be detailed oriented, proactive, shows initiative, and has a deep desire to break the design
- Excellent debug skills of test bench, models, tests, RTL, scripts and tools
- Expert understanding of code and functional coverage-driven verification closure.
- Ability to set up and deploy verification strategies based on directed testing, randomization, assertions, corner case and architectural performance testing to achieve system performance and coverage goals
- Experience architecting verification components to be reused at sub-system and chip level.
- Familiar with scripting languages
- Excellent communication and teaming skills
- Strong technical breadth in technologies such as DDRx, HBMx, 10G/40G Ethernet
- Strong Object oriented programming experience/skills
- Low Power Verification Methodologies
- Background in scripting for automation of verification methodologies & flows
- Proficiency in Perl, Unix Make, Unix Shell Scripts
- Post Silicon lab Validation
- Advanced Behavioral Modeling, mixed signal verification a strong plus
Rambus offers an extremely competitive compensation package, which includes a strong base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.
Rambus creates cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting. Our chips, customizable IP cores, architecture licenses, tools, services, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile, consumer and media platforms. At Rambus, we are makers of better. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/ .
To apply for this job please visit tinyurl.com.