Warning: count(): Parameter must be an array or an object that implements Countable in /home/anton702/public_html/wp-includes/post-template.php on line 317

DFT Structural Design Engineer...

DFT Structural Design Engineer

Santa Clara, CA 95052 2016-11-04 - –

intel Intel

Job Description

DFT Structural Design / STA Flow Development EngineerSeeking a highly motivated, team-oriented engineer to drive development of Design for Test (DFT) insertion, synthesis, power optimization and timing analysis flows. In this position, you will be involved in the development and refinement of the physical construction and timing flows for DFT insertion into soft and hard IPs and SoCs, spanning from small IoT devices to large server processors.The candidate should have experience in DFT, deep knowledge of scan insertion and ATPG methodology, memory test insertion and methodology. Knowledge of JTAG, 1687, boundary scan and IO testing would be a plus. Digital design experience related to SoC and IP design is required, especially in the areas of synthesis, timing analysis, power optimization, and clock tree construction. Seeking candidates with experience in DFT insertion and analysis tools such as DFT Compiler, Design Compiler, Power Compiler, Mentor Testkompress, Tessent Memory BIST, Primetime, ICC and clock tree synthesis. Ability to develop TCL based scripts for EDA DFT tools is required.


MinimumQualifications and skills: You should possess a Masters or Bachelor's degree inElectrical/Electronics/Computer Engineering, with 3+ years relevant experience in the industry. Candidateshould have 3+ years of experience with the following: -Experience in circuit design fields: high-speed digital circuits, Timinganalysis, and Power optimization. Experience with VLSI circuit design fundamentals (CMOS, high-speed, low-powerdigital circuits; concept of timing and physical design convergence; layoutknowledge). -Experience in VLSI design, EDA synthesis tools and methodologies Preferred Qualifications: DFT insertion, synthesis, power optimization and timing analysis High-level programming skills of scripting languages (Perl, Python) Experience with System on a chip integration Knowledge of computer/CPU architecture*LI-USA-BH1 Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

To apply for this job please visit tinyurl.com.